1. Field of the Invention
The present invention relates to a data packet shortening method and device, which makes it possible to reduce the length of a data packet in an electronic computer.
2. Description of Related Art
In microcomputers, when a process is being carried out which uses data stored in a memory device, the process of reading particular data is carried out by sending a read request related to a particular address of the memory device. In serial processing computers it is not generally possible to read data which has not yet reached the memory device. Where serial processing computer systems operate such that commands of a program are executed separately in separte devices there are circumstances in which an attempt is made to read information which has not yet arrived in the memory device. In such systems, it is necessary to have a construction whereby the read request is delayed and processed after the missing data has arrived in the memory device.
FIG. 1a is a diagram illustrating the relationship between a delay management device, a processing device, and a memory device. The memory device is capable of delaying read requests. The memory device 100 comprises four parts, that is a distribution (allocation) section 100a, a memory section 100b, a delay (defer) processing section 100c and a clear section 100d. Channels 101 and 102 enable data to be sent from the processing device 103 to the memory device 100, and from the memory device 100 to the processing device 103 respectively.
The exchange of data between the processing device 103 and the memory device 100 is entirely by the sending of individual data packets (hereinafter referred to as "tokens"). When the distribution section 100a of the memory device 100 receives a memory space request token 104, it sends a start address for the requested space depending on the requested size in the form of a token 107. The memory section 100b receives a write token 105 and a read request token 106. In accordance with the former it enters a parameter V into address A, and in accordance with the latter, it reads the contents V of the address A and sends this to the processing device 103 as a data token 108. For tokens other than the write token a response is required, and responses are identified by parameter Ra. The delay processing section 100c and the clear control section 100d do not deal directly with the communication of tokens to and from the processing device 103. The delay processing section 100c carries out the processing of read requests relating to data which has not yet arrived in the memory section 100b, and the clear control section 100d carries out the process of making memory space available when it is no longer being used.
The different types of tokens are distinguished by a code. FIG. 1b illustrates an example of the construction of each of the tokens. Numerals 464 to 468 correspond to 104 to 108 respectively in FIG. 1a. Each token has four fields, namely a code field 451, a second field 452, a third field 453, and a fourth field 454.
The code field 451 is used to distinguish between the different kinds of token, and in the examples of FIG. 1b the code field has four bits, which can identify up to sixteen different kinds of tokens. The second, third and fourth fields, 452 to 454, all comprise twenty four bits in the illustrated examples for the sake of simplicity, but these numbers may be adapted to the needs of the particular system. The shaded areas in the diagrams represent fields which are not being used.
FIGS. 2a, 2b and 2c are diagrams which serve to explain in more detail the function of the memory section 100b and the delay processing section 100c shown in FIG. 1a. In FIG. 2, channels 201 and 202 serve to convey tokens to and from the memory section 100b respectively. Each address within the memory section 100b consists of a flag field and a data field, the flag field comprising a valid flag 203 which shows whether or not there is any significant data stored within the data field, and a delay flag 204 which shows whether or not a read request relating to that address has already been delayed. That is to say, when data is entered in the data field 205 by a write token, the valid flag 203 becomes "1", and when that address is returned to its original state the valid flag becomes "0". When a read request token has been delayed, the delay flag 204 becomes "1" and when data has been entered into the address, or the word has reverted to its original state, the delay flag becomes "0".
Referring to FIG. 2a, when a read request token 206 which corresponds to an address A reaches a memory section 100b, the response of the memory 100b depends on the state of the valid flag within the address A. That is to say:
1. If the valid flag is "1", then as shown in FIG. 2b, the value V stored in the data section of the address A is read, the value V is joined to the identifier parameter Ra of the read request token, and the result sent out as a data token 207.
2. If the valid flag is "0", then as shown in FIG. 2c, the read request token is housed in a token housing field 207 of an arbitrary free address (for example address Q) within the delay processing section 100c. However, for the sake of memory space economy, the address parameter A is deleted, but this deletion is not necessary. Data is entered in a linking field 208 of address Q. This data is represented by an asterisk in the drawings, and shows that in this case it is a first delay token relating to the address A. A token store address pointer Q is stored within the data field of address A to which the delayed read request relates. The delay flag 204 has "1" entered in it.
In this device more than one read request token can arrive relating to a single address of the memory section 100b. Accordingly several tokens can be delayed which relate to one address. Referring to FIGS. 3a and 3b, in such circumstances the delay tokens are stored as a series. In FIG. 3a, numerals 301 to 305 identify elements which correspond to components 201 to 205 of FIG. 2a. The series fields for the addresses in the delay processing section 100c are used to arrange the delay tokens in a series. When a write token 307 arrives in address A then, referring to FIG. 3b, the delay tokens which are associated with address A are all released. The value V is entered into the data field of the address A of the memory section 100b, and at the same time "1" is entered into the valid flag 303 and "0" is entered into the delay flag 304. The address Q3 previously stored in the data field of address A is reviewed, and then address Q2 (stored at address Q3), and then address Q1(stored at address Q2). The series of three delayed token can thus be regenerated. The value V which is now stored at address A is joined with the stored identifiers Ra3, Ra2 and Ra1 to form data tokens 308 to 310 which are sent to the processing device. The address Q1 to Q3 which stored the delay tokens become free addresses and can be used for subsequent delay tokens.
In the above-described process, during the time that the delay token series process is being conducted, it is not possible to read or write data, and this means that the system is slow. The problem cannot simply be solved by separating the memory section 100b and the delay processing section 100c as shown in FIG. 4a and making use of the device explained with reference to FIGS. 2a to 2c. That is to say, in systems like that shown in FIGS. 4a and 4b, operation of the memory section 100b and the delay processing section 100c at the same time gives rise to new problems. These problems are explained below with reference to FIGS. 4a to 4e.
In FIG. 4a, numerals 401 to 405 correspond to 301 to 305 respectively of FIG. 3a, and identify elements which function in the same way. Channels 409 and 410 convey tokens from the delay processing section 100c to the memory section 100b and from the memory section 100b to the delay processing section 100c respectively. In FIG. 4a, two read request tokens relating to address A are shown as having been delayed, and furthermore a new read request token 411 has arrived at the address A. The results of this situation are described below.
1. The read request token 411 is delayed so that the valid flag 403 of the address A is "0", and as in FIG. 4b, it becomes delay token 412 which is sent to the delay processing section 100c. The delay token 412 includes the start address Q2 of the delay series. The address Q2 is stored in the address A.
2. When the delay token 412 arrives at the delay processing section 100c, as shown in FIG. 4c the token 412 is stored in an arbitrary free word (for example Q3) and at the same time a new start address token 413 is sent to the memory section 100b. The token 413 includes the new start address Q3 of the delay token series which must be communicated to the memory section 100b.
FIG. 4f shows the make-up of the tokens DREAD and NQA. In FIG. 4f, fields 751 and 754 correspond to the fields 451 to 454 in FIG. 1b. The shaded parts of the diagram are fields which are not used.
Assuming that a new read request token relating to address A arrives at the same time at the memory section 100b, the following possibilities arise:
3. If the token 413 arrives before the token 414, then the memory 100b enters the parameter Q3 included in token 413 into the address A. Then as shown in FIG. 4d, the pointer stored in address A indicates the start of the delay series, and token delay processing can continue normally.
3'. If the token 413 arrives after the token 414, the token 414 is delayed and as shown in FIG. 4e it becomes a token 411. The parameters of the delay token 411 include the value Q2, and although the token 411 is housed within the delay processing section 100c there are two tokens which are associated with the address Q2, and the normal series cannot be followed.
To deal with the above problem, the device illustrated in FIG. 5 has been devised. Referring to FIG. 5, which is a block diagram, a processing device 1 is shown which corresponds to the processing device 103 of FIG. 1a. A memory section 2 and a delay processing section 3 correspond to the memory section 100b and delay processing section 100c of FIG. 1a. Communication devices 4 and 5 convey tokens between the processing device 1, the memory section 2, and the delay processing section 3, and these devices 4 and 5 correspond to the channels 101 and 102 in FIG. 1a.
The memory section 2 comprises a buffer 2a which temporarily holds tokens which are received from the communications device 4. A control section 2b identifies the different kinds of tokens that are received and, depending on their type, the parameters of the tokens are stored in a memory 2c or the contents of the memory 2c are read. A buffer 2d serves the purpose of sending tokens to the communications device 5 from the control section 2d.
In the delay processing section 3, a buffer 3a temporarily holds tokens which are received from the communications device 4. A control section 3b distinguishes between the different kinds of received tokens and depending on the type of these tokens it either stores their parameters in a memory 3c or reads the contents of the memory 3c. A buffer 3d serves to send tokens from the control section 3b to the communications device 5.
Referring to FIG. 6, this serves to illustrate an important feature of the control section 2b and the memory section 2c of the memory 2. The memory section 2c stores the addresses Q3, Q4, Q5. . . QN etc. of free space in the memory section 3c shown in FIG. 1. The free address space in the memory 3c which is available for use is indicated by a stack pointer 20. A buffer 21 supplies fresh addresses which have become available. Thus free addresses accumulate and are used as required.
A method of delay processing in which a normal series of single addresses for delay tokens is built up will now be explained. The arrangements shown in FIGS. 5 and 6 are simply examples of the possible constructions, which need not be limited to for example the buffers 2a, 2d and the control section 2b. The operation of the described arrangement is however described with reference to FIGS. 7a to 7g.
Referring to FIG. 7a, a free memory space 30 in the memory 2c of the memory section 2 includes space 30a in which are stored the addresses of free space in the memory 3c shown in FIG. 6. A valid flag 30b and a delay flag 320c correspond to flags 403 and 404 as shown in FIG. 4a. Numeral 31 indicates free memory space within the memory 3c of the delay process section 3. Channels 32, 33, 34 and 35 are provided to convey tokens and correspond to the communication devices 4 and 5 shown in FIG. 5.
Referring to FIG. 7a the operation of the delay processing device shown in FIGS. 5 and 6 will now be explained. FIG. 7a illustrates the situation, as also shown in FIG. 4a, in which delay of two read request tokens has already occurred, and a new read request token 512 is arriving at the memory section 2. In contrast to FIG. 4a however, the address space 30a is provided for storing free address in the delay processing section 3. A free address token 511 includes a free address in the delay processing section 3 as a parameter, and delivers that address to the address space 30a. This is described below:
1. When the memory section 2 receives the free address token 511 and the read request token 512, the valid flag 30b is "0", and thus as illustrated in FIG. 7b, the read request is turned into a delay token 513 and sent to the delay processing section. The address parameters are removed from the read request token 512, and by adding the value Q2, which is held in the address A, and Q3, which is the parameter held by the free address token, the delay token 513 is made up. Then the free address Q3 is stored in the address A.
2. When the delay token 513 arrives at the delay processing section 3, as shown in FIG. 7c, the other parameters of the delay token are stored in the address Q3. The parameter Q2 is housed in a series field. In the address A of the memory section 2, the address Q3 has already been entered, so the delay series is complete.
3. The delay processing section 3 then makes a new free word token 514 and sends this to the address section 30a of the memory section 2 for use in a subsequent token delay process.
With the above-mentioned procedure, the problems outlined with reference to FIGS. 4a to 4f do not occur. That is to say, even in the situation such as that shown in FIG. 1b where a delay token 513 has not yet arrived at the delay processing section 3, the memory section 2 can still effectively delay a token related to the address A. For example, in the situation shown in FIG. 7b, when a token related to address A is delayed, the delayed token should have the parameters Q4, Q3 and Ra4 (token 520 in FIG. 7d). Q4 is a free address in the delay processing section 3 previously entered in the address space 30a of the memory section 2. When this token arrives in the delay processing section 3, it is quite clear that it forms a series. For example, even if the token 520 overtakes the token 513 of FIG. 7d, the order of the series is not changed and a normal series is completed once the token 513 has arrived.
On the other hand in the situation shown in FIG. 7c, when a write token relating to address A arrives, delay tokens which are related to the address A are released as described hereinbelow.
4. When the memory section 2 receives the write token, it reviews the delay flag 504, and because the value of this is "1" it knows that there is at least one delay token associated with the address A. Thus, at the same time as the value V is entered into address A, the release request token 516 is generated. Then the valid flag 30b is changed to "1", and the delay flag 30c is changed to "0".
5. The release request token 516 includes the address A and the value Q3 which as shown in FIG. 7e, and delivers this data to the delay processing section 3.
6. When the delay processing section 3 receives the release request token 516 it knows from its parameter Q3 the start address of the series to be released. The delay processing section 3 joins the address parameter A to the delay tokens which belong to this series, and generates read request tokens identical to the original read request tokens before they were delayed, that is token 517 to 519 in FIG. 7f. These read tokens are sent to the memory section 2. Then each of the address at which the delay tokens were stored in the delay processing section 3 becomes a free address.
7. When the read request tokens arrive at the memory section 2, they read the address A and join the value V to the identifier (Ra.sub.3, Ra.sub.2, Ra.sub.1) address and send corresponding data tokens to the processing device 1.
The tokens READ and WRT in FIGS. 7a to 7f have exactly the same form as the READ and WRT tokens illustrated in FIG. 1b.
The form of the tokens DREAD, FA and RRQ which occur in FIG. 7a to 7f, are shown in FIG. 7g (the shaded sections in the diagrams represent fields which are not used). In the same diagram, 551 to 554 correspond to 451 to 454 in FIG. 1b.
The token DREAD in FIG. 7g is different from that of FIG. 4f, in that it uses one more field. FA corresponds to NQA in FIG. 4f, but it uses one less field.
Since the read request tokens 517 to 519 released from the delay processing section 3 have exactly the same form as the delayed read requests to which they relate, there is no need to distinguish in the memory section 2 whence these tokens came. For the sake of simplicity of explanation, referring to FIG. 7a, free token 511 is sent to the address space 30a of the memory section 2 at the same time as the read request token 512. Even if several free address tokens have accumulated in the address space 30a this is all right. Each time the delay processing section 3 receives a delay token, if it sends a free word token to the memory section 2, the accumulation of free word tokens in the memory section 2 is maintained.
In the process described with reference to FIG. 7a to 7g, the delay token 513 has three parameters. That is to say, the address Q3 into which is to be entered the token 513, the start address Q2 of the already existing token series, and the identifier address Ra3. This means that the data packet of the token which holds all three parameters is long, and the token channel requires expensive hardware. The address required to identify empty space in the memory device 31 for use with the delay tokens tends to be large, and the bit packages for entering addresses Q3 and Q2 are equally large.
It is an object of the present invention to obviate or mitigate the above problems by shortening the length of the tokens.